Lab Power supply ADC and Output Voltage

So I fixed the error in the amplifier that converts the output voltage down to the range required by the ADC and fitted the ADC, voltage reference and crystal. I soldered the sense and output wires together but I was *still* seeing problems with output voltage fluctuations under load.

ADC

When soldering the ADC I took a slightly different approach. Initially I used solder paste on all the components but found I couldn't dispense it finely enough for the fine pitch components so went back to hand soldering. Keeping the chip aligned while hand soldering is tricky so I revisited using paste. This time I applied flux to the board and then held the solder paste syringe nearly vertically so the tip was flat to the tracks. I gently moved it up and down and the flux would slightly dissolve the binders in the paste so I could smear on a smaller amount. This worked really well and gave me a pretty neat joint after I heat-gunned it.

I fitted the reference, the crystal, the crystal capacitors and the bypass caps as well as the ADC. I powered it up and saw a nice steady 2MHz signal on the oscilloscope. I re-enabled the software to read from the ADC and I modified the code to add a command to read the ADC count rather than the converted voltage. This would make calibration easier.

The output looked *really* good. Before I found the ADC would give dodgy results when switching between the two channels but there was no sign of this. Also the ADC seemed a bit slow but that also was gone and the response comes back without delay. The ADC counts barely vary and even when they do it is less than a single count so the noise is very low. Even without calibration the values looked very consistent.

I did a calibration run where my python script steps the voltage (by stepping the DAC count through 32 steps evenly divided across the count range) and then reading both the output voltage on the Agilent 34461A and the ADC count. The results are stunning - here is a graph of voltage vs count:

I then took each voltage and divided it by the count (effectively measuring the volts per step). The first one was a bit off but otherwise they too were *very* good.

If I remove the first one from the data you can see the variation more clearly:

The variation between the top and bottom value is less than 1.5ppm. Impressive!

Output Voltage

Previously I noted that if I moved the output terminals around, the voltage variation under load pretty much cancelled out. While testing the ADC I noticed that under load the output voltage reading varied from the unloaded value. I decided it was time to tackle this problem once and for all!

The power and sense wires each had a round spade terminal soldered and crimped to the end of them, The connection between them was just by contact and the pressure of the retaining nut. I made new sense wires and soldered these onto the same lug as the power wires so there was no contact resistance issue and hopefully when I wiggled the wires nothing would change!

When I powered it up the output was much more consistent and still close to the calibration setting. 10V came out as 10.001V. When I enabled a 4A load (from the dummy load) the voltage went up to 10.025V (25mV increase).

When I tried tracking this down before it was really hard as I felt like everything was in motion. This time wasn't so hard - under load the voltage at the S+ screw terminal was about 10mV different from the V+ and similarly the S- and V- differed. The difference between the S+ and the voltage at the banana plug was tiny (less than 1mV). In fact I measured the difference between the top of the banana and the bottom (where the wires connect) and it came out to 0.7mV.

This all makes sense - the 10mV difference is due to the wire resistance and the sense voltage is consistent with the output voltage. There is a small difference between the voltage at the back of the banana (where I am sensing from) and the front but nothing to get upset about.

On a hunch I thought it might be my old friend the grounding problem. I attached the negative probe of my DMM to the virtual ground (the inboard end of the 10m shunt) and measured the difference in ground potential to various points around the board. 

The ground at U1 (the main opamp package that drives the voltage and current control loop) varied by 5mV! There is a layout problem as I grounded this from a different point along the fat ground conductor going to the output:

I soldered a wire from the correct ground point to the bypass cap near the chip. I can't totally fix this as it is still connected to the fat track but it meant the voltage only varied by about 1mV instead of 5mV.

So then where is this 25mV difference coming from? I noted that the ADC reading matched the output voltage both when under load and not under load. This means the differential amp that reads the output voltage must be right. So then why does the output vary?

I measured the output of the amplifier that takes the 0-5V from the DAC and converts it to 0-30V for the control loop. That too was varying by nearly the exact same amount as the output! I measured the difference in the DAC output when loaded and un-loaded and it was tiny - would barely account for 1mV of the output difference.

This amplifier looks like this:

I measured the voltage at the ground point on R7 and found it varied by a lot! (6mV). This would just about account for the problem.

Searching the board I found it too was badly connected to ground so I ran another wire to that point. That pretty much nailed it! The output now varies by around 2mV under load. 1.4mV of this is accounted for by the resistance of the banana jacks. The rest is probably due to the fact that I can't cut the connection to the fat track.

That's more like it!

An interesting effect of fixing the ground issues is that the output noise fell considerably. This is the output at 10mV per division, trigger source is line (as it tends to be in time with the line frequency) and a 4A load.

 

I did this again but used my Tektronix 475 (as it is better at low voltages). Here is the output with 2mV per division, line triggering and no load

And here it is with 4A load

So it looks like the noise went from around 2mV P-P to about 6mV p-p. Still *very* low. Also the measurement really needs to be done with coax to the terminals.

Next

I want to make sure the serial interface is fast enough for the GUI so it is time to hook up some GUI code (more on this later). I still have a nagging problem in the pre-regulator when under very low frequency pulsed load. Till next time!