Playing with Buck Converters

I wanted to learn about switching power regulators and while I get the general principles, I have no idea how to control one or set one up. I thought I'd start with a simple MC34063 and bought some from ebay.

Buck Maths - Simple

This analysis is not unique and with any luck it is actually right! I hope it is of use to someone and maybe even me in the future when I forget how to do these calculations! First things first - here is a simplified circuit for a buck converter.

I've omitted some important things like the controller and the feedback but in essence the way this works is:

• The controller turns on the PMOS transistor which causes current to start flowing through L1 and the load R1 as well as charging up C1. The diode D1 is reverse biased so no current flows through there at the moment.
• The current through the inductor ramps up linearly
• At some point the transistor switches off and the back-EMF through the inductor keeps current flowing into R1 and C1. Now the diode D1 is forward biased and completes the circuit with the output. The current now linearly ramps down through L1.
• The cycle repeats

The net result is the output voltage is lower than the input and while there is a transistor in the circuit, the transistor is only ever fully on or fully off. This means the resistive losses through the circuit are reduced compared with a linear regulator and most of the input power is transferred to the load.

So the transistor is switched at some period \(T\) and the time the transistor is on vs off is not the same. The proportion of the time the transistor is on is the duty cycle \(D\). The input voltage is \(V_{in}\) and the desired output is \(V_o\). The output voltage will vary but we assume that the average output will be the target \(V_o\).

Hysteretic Control

The way the MC34063 works is quite simple but quite limited. There is an internal oscillator that generates a ramp up and then ramp down at a frequency determined by an external capacitor. There is a comparator that triggers when the sampled output voltage (sampled via a resistor divider network) matches an internal reference.

During the ramp up time, if the sampled output drops below the reference the IC turns on the current to the inductor. The current remains on until the end of that cycle where it turns off. Usually the voltage won't have dropped far enough until after the start of the up-ramp so the longer it takes to fall the later the IC turns on and the shorter the on period. This serves to regulate the output voltage.

If the load is light however the IC may not turn on during the whole cycle. In fact if the output is unloaded it can take a long time between cycles.

As the output does not turn-off until the cycle is finished, there is nothing to stop it over-shooting by a lot before it turns off.

The IC has one additional trick up its sleeve and that is to fold-back the voltage under excessive load. The IC sense the current at the input and once this exceeds a threshold, the IC will hasten the up-ramp so the cycle finishes earlier. In the extreme case of a gross over-load the cycle will finish very quickly and minimize the output voltage. You can configure the max current by choosing the value of the sense resistor.

Duty Cycle - Simple

The the voltage over an inductor follows the equation

\[V = L\frac{di}{dt}\]

We know the voltage over the inductor when it turns on will be \(V_{in} - V_o\) so we know that the slope of the current increase through the inductor will be \(\frac{V_{in}-V_o}{L}\) and the amount the current increases will be \(\frac{V_{in}-V_o}{L}DT\).

When the switch turns off the inductor back-EMF will keep current flowing but it will decrease. The voltage across the inductor this time will just be \(V_o\) (neglecting the voltage drop of the diode) and so the downward slop will be \(\frac{V_o}{L}\). The down-slope occurs for a time period of \((1-D)T\) seconds so the total decrease in current will be \(\frac{V_o}{L}(1-D)T\)

Because we are in a steady-state, the increase in current during the on period must equal the decrease in current during the off period and hence we can write

\[\frac{V_{in}-V_o}{L}DT = \frac{V_o}{L}(1-D)T\]

We can simplify this a bit by cancelling the L and the T and we can expand the brackets to get

\[V_{in}D-V_oD = V_o-V_oD\]

Now we cancel the \(V_oD\) as this appears on both sides and get

\[V_{in}D= V_o\]

Then re-arrange to get

\[D= \frac{V_o}{V_{in}} \tag{1}\]

That's pretty damn cool! The buck converter drops the input voltage in proportion with the duty cycle.

Duty Cycle - Better

Lets try this again but this time we want to include the diode and transistor drop.

This time lets assume the switch has a voltage drop of \(V_{sw}\) and the diode has a forward voltage drop of \(V_d\).  When the switch is on we can ignore the diode as before but now if we apply KVL to the loop from the input voltage to the output we get:

\[V_{in}-V_{sw}-L\frac{di}{dt}-V_o=0\]

Where \(\frac{di}{dt}\) is the slope of the inductor current during the on-period. Re-arranging we get

\[\frac{di}{dt}=\frac{V_{in}-V_{sw}-V_o}{L}\]

If we define \(t_{on}\) to be the amount of time the switch is on and \(t_{off}\) the time the switch is off (so \(D=\frac{t_{on}}{t_{off}}\)) then the rise in inductor current (\(I_p\) is:

\[I_p=\frac{V_{in}-V_{sw}-V_o}{L}t_{on}\]

Similarly for the period the switch is off

\[V_d+L\frac{di}{dt}+V_o=0\]

\[\frac{di}{dt}=\frac{V_o+V_d}{L}\]

During the off period the current starts at \(I_p\) and reduces for the time \(t_{off}\) so:

\[I_p=\frac{V_o+V_d}{L}t_{off}\]

Equating the two equations for \(I_p\) we get

\[\frac{V_{in}-V_{sw}-V_o}{L}t_{on} = \frac{V_o+V_d}{L}t_{off}\]

And therefore:

\[\frac{t_{on}}{t_{off}}=\frac{V_o+V_d}{V_{in}-V_{sw}-V_o} \tag{2} \]

Peak Current

So what is the value of  \(I_p\)? Well it has to be the average of the current over the whole cycle. So if we integrate the current during \(t_{on}\) and during \(t_{off}\) and divide by \(T\) then this should be the average. As the current increases linearly to \(I_p\) and then decreases linearly to the starting point again we know that the average current \(I_{avg}\) can be calculated as:
\[I_{avg} = \frac{I_p \frac{t_{on}}{2} +I_p \frac{t_{off}}{2}}{T}\]
\[I_{avg} = \frac{I_p t_{on} +I_p t_{off}}{2T}\]
\[I_{avg} = \frac{I_p ( t_{on} + t_{off})}{2T}\]
As \(T = t_{on}+t_{off}\) then:
\[I_{avg} =\frac{ I_pT}{2T}\]
\[I_{avg} = \frac{I_p}{2} \tag{3} \]
So that's pretty useful - the peak current is twice the average output current.

Inductor

So if we choose a frequency of operation \(F\) and we realize that \[F = \frac{1}{t_{on}+t_{off}}\] then we can work out \(t_{on}\) and \(t_{off}\) based on the ratio we calculated in equation 2.

Then re-arranging the formula for \(I_p\)

\[I_p = \frac{V_{in}-V_{sw}-V_o}{L}t_{on}\]

We can work out the minimum inductor value as follows:

\[L = \frac{V_{in}-V_{sw}-V_o}{I_p}t_{on}\tag{4}\]

Or alternatively if we know have an inductor on hand of size L we can work out \(t_{on}\) then work out \(t_{off}\) from the ratio and therefore \(F\).

Capacitor

Ok this gets harder - so the current through a capacitor is \(i=C\frac{dv}{dt}\). The output is drawing \(I_{avg}\) but the inductor current ramps from below this to above it. The difference in current flows either into our out of the output capacitor.

The inductor current ramps linearly to \(I_p\) so the current at any point from the start of the ramp is \(i_1 = \frac{\frac{1}{2}I_pt}{\frac{t_{on}}{2}}\). Similarly the current during the ramp down can be calculated as \(i_2 = \frac{\frac{1}{2}t}{\frac{t_{off}}{2}}\). The voltage change can be calculated from the integral of the curent. The peek-to-peek ripple voltage includes the positive and negative ripple so this is calculated from

\[V_{ripple} = \frac{1}{c}\int_0^{t_1} i_1 dt + \frac{1}{c}\int_{t_1}^{t_2} i_2 dt \]

and \(t_1 = \frac{t_on}{2}\), \(t_2-t_1 = \frac{t_off}{2}\) So the integral becomes

\[V_{ripple} = \frac{1}{c}\left|\frac{I_p}{t_{on}}\frac{t^2}{2}\right|_0^{t_1} + \frac{1}{c}\left|\frac{Ip}{t_{off}}\frac{t^2}{2}\right|_{t_1}^{t_2}\]

If we substitute \(t_1\) and \(t_2-t_1\) we get:
\[V_{ripple} = \frac{1}{c}\left(\frac{I_p t_{on}^2}{8t_{on}} + \frac{I_p t_{off}^2}{8t_{off}}\right)\]

\[V_{ripple} = \frac{I_p(t_{on}+t_{off})}{8c}\]

And  \(t_{on} + t_{off}\) is basically the period. This is equal to \(\frac{1}{f}\) so then  we can write this as:
\[V_{ripple} = \frac{I_p}{8Cf}\tag{5}\]

I won't try and calculate the input capacitor here. I think it is a matter of choosing a capacitor value and ESR such that the input ripple is below some desired maximum. I suspect you need to subtract the ripple from the minimum input voltage and use that as the minimum input for the buck design. For now I am just choosing something I think will be big enough.

Test Circuit

To try this out I am using a MC34063 which is a hysteretic (i.e. bang-bang) converter. It's a pretty basic part but will do to for building a basic circuit.

The plan is to build a converter that takes 12V in (minimum) and outputs 5V. at a maximum of 300mA (this is the close to the limit of the chip but also the limit of my inductor). Also we want to get 10mV of ripple or less.

I am using a EGP20D fast diode which has a forward drop of around 0.5V. The chip datasheet spec has the switch drop as 0.8V. Using (2) we calculate:

\[\frac{t_{on}}{t_{off}}=\frac{5 + 0.5}{12 - 0.8 - 5.0}\]

\[\frac{t_{on}}{t_{off}}=0.89\]

We have a 100uH inductor so we want to adjust the frequency to suit this. We re-arrange (4) as follows:

\[t_{on} = \frac{I_p}{V_{in}-V_{sw}-V_o}L\]

And calculate this as

\[t_{on} = \frac{600e-3}{12.0-0.8-5.0}100e-6\]

\[t_{on} = 9.7\mu s\]

\[t_{off} = \frac{9.7e-6}{0.89} = 10.8\mu s\]

\[f = \frac{1}{t_{on} + t_{off}} = 48kHz\]
We check that \(\frac{t_{on}}{t_{on}+t_{off}} < 0.857\) and in our case it is 0.47

Then to calculate the output capacitor we use (5) and calculate:

\[c = \frac{600e-3}{8 \times 10e-3 \times 43e3}\]

\[c = 174\mu F\]

But we choose \(c = 200\mu F\)

The MC34063 also requires a current sense resistor and can fold-back the voltage if the current is exceeded. You choose a resistor so that the voltage over the sense resistor is 0.33 at max current. We choose \(\frac{0.33}{0.6} = 0.5\Omega\)

There are more calculations to work out the sense resistor and the resistor divider for measuring the output voltage but these are pretty easy so I won't go through them all here. The only thing was I didn't have the resistors I needed so used 1.1K and 3.9K which give out output voltage of about 5.3V


Here is the test circuit

I tried proto-typing this on breadboard but while it worked the noise was horrendous. I tried again by dead-bugging the circuit on a piece of copper but again the leads were too long and the noise was bad. I decided to home-brew a single-sided PCB like this:

Results

This image shows the timing capacitor waveform. You can see the ramp-up is \(9.2\mu s\) which is close to the 9.7 designed. The bump in the ramp up is caused by the output turning on. The overall frequency is much higher than the 48kHz design however and this makes sense from the timing waveform. The ramp down is alway 1/6 of the ramp up period which here is 1.5uS. Consequently the total period is around 94kHz. I think I have confused \(t_{on}\) with max \(t_{on}\). This will need some more thinking if I ever build one of these again.

In this trace the module is providing 300mA to dummy load. The green waveform is the output and the yellow is once again the timing capacitor. The cursors show that the output ripple is around 50mV - much higher than the 10mV predicted. Part of the reason for this difference is the ESR of the output capacitor which is \(0.1\Omega\). This results in a 30mV ripple just as a result of the ESR. This combined with the predicted ESR is pretty close to the design.

The on time however seems far to low compared with what was calculated. The on/off ratio is around 50% compared with the calculated 90%. Amusingly it is quite close to the crude approximation of 5.3/12. Also the on time is quite low at 5.2uS compared with the 9.7 calculated for 300mA. Not really sure why that is.

You can see the effect of the hysteretic control on the load regulation in the image below. In this image the output is unloaded so the system will very occasionally fire a single pulse to re-charge the output. Without any load the voltage rises far above the design and then takes many cycles to come back down to a level where another pulse is fired.

In this trace the output voltage is shown in yellow and the current flowing in the electronic load is show in green. The electronic load is set to draw power in pulses from the supply. When the load turns on it takes quite a few cycles before the voltage drops to a level where the power supply starts pulsing the inductor. 

Conclusion

So it's been an interesting foray in DC-DC converters and while it was a good start I think I am missing the interesting bits. The much harder problem looks to be the control loop that usually regulates the output (rather than the bang-bang controller implemented by this chip).